----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:32:24 12/08/2006 
-- Design Name: 
-- Module Name:    UART_Tx - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UART_Tx is
    Port ( clk : in  STD_LOGIC;
           uart_tx_in : STD_LOGIC_VECTOR (7 downto 0);
			  uart_tx_out : out  STD_LOGIC;
			  tx_enable : in STD_LOGIC;
			  tx_done : out STD_LOGIC);
end UART_Tx;

architecture Behavioral of UART_Tx is

signal tx_counter : integer;
signal delay_counter : integer;

begin

UART_Tx : process(clk)
begin
	if rising_edge(clk) then
	
		if tx_enable = '1' then
			if delay_counter = 1008 then
			if tx_counter = 9 then
				tx_done <= '1';
				delay_counter <= 0;
				tx_counter <= 0;
			else
				delay_counter <= delay_counter + 1;
				if delay_counter >= 1000 then
					tx_counter <= tx_counter + 1;
				end if;
			end if;
			
			if delay_counter < 1000 then
				uart_tx_out <= '1';
			elsif delay_counter >= 1000 then
				if tx_counter = 0 then
					uart_tx_out <= '0';
				elsif tx_counter > 0 then
					uart_tx_out <= uart_tx_in(tx_counter-1);
				end if;
			end if;
		else
			uart_tx_out <= '1';
			delay_counter <= 0;
			tx_counter <= 0;
			tx_done <= '0';
		end if;
	
	end if;
end process UART_Tx;

end Behavioral;

